Electronic systems often include a clock buffer that may be used in a variety of applications such as with clock and data recovery circuits or serializers and de-serializers (e.g., MUX/DEMUX circuits). The clock buffer may be tuned to a corresponding clock signal frequency to reduce the power consumption of the clock buffer. However, in some instances, the frequency of the clock signal input into the clock buffer may vary.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.